Finfet with dual work function metal

ABSTRACT

An embodiment of the invention may include a method for of forming a semiconductor device and the resulting device. The method may include forming a gate dielectric on a gate region of a substrate. The method may include forming an inner dummy gate on a first portion of the gate dielectric. The method may include forming an outer dummy gate adjacent to the inner dummy gate on a second portion of the gate dielectric. The method may include forming spacers adjacent to the outer dummy gate. The method may include removing the outer dummy gate and depositing a first work function metal. The method may include removing the inner dummy gate and depositing a second work function metal.

BACKGROUND

The present invention relates to semiconductor fabrication, and morespecifically, to MOSFET gate manufacturing techniques.

FETs are commonly employed in electronic circuit applications. FETs mayinclude a source region and a drain region spaced apart by asemiconductor channel region. Metal-oxide-semiconductor field-effecttransistor (MOSFET) are a common type of FET. In planar FETs, thesemiconductor channel region may be a semiconductor substrate. InFinFETs, the semiconductor channel region may be a semiconductor fin. Agate, potentially including a gate dielectric layer, a work functionmetal layer, and a metal electrode, may be formed above the channelregion. By applying voltage to the gate, the conductivity of the channelregion may increase and allow current to flow from the source region tothe drain region.

FinFETs may provide solutions to field effect transistor (FET) scalingproblems at, and below, the 22 nm node. FinFET structures include atleast one narrow semiconductor fin as the channel region of the FET andare gated on at least two sides of each of the at least onesemiconductor fin. FinFETs including more than one fin may be referredto as multi-fin FinFETs. FinFETs may be formed on bulk substrates toreduce wafer cost and/or enable formation of certain devices in the bulksubstrate.

BRIEF SUMMARY

An embodiment of the invention may include a method for of forming asemiconductor device. The method may include forming a gate dielectricon a gate region of a substrate. The method may include forming an innerdummy gate on a first portion of the gate dielectric. The method mayinclude forming an outer dummy gate adjacent to the inner dummy gate ona second portion of the gate dielectric. The method may include formingspacers adjacent to the outer dummy gate. The method may includeremoving the outer dummy gate and depositing a first work functionmetal. The method may include removing the inner dummy gate anddepositing a second work function metal.

An embodiment of the invention may include a semiconductor device. Thesemiconductor device may include a gate dielectric located on asubstrate, wherein the gate dielectric defines a gate region of thesubstrate. The semiconductor device may include a first work functionmetal located on a first portion of the gate dielectric. Thesemiconductor device may include a second work function metal located ona second portion of the gate dielectric, wherein the first work functionmetal sandwiches the second work function metal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a depicts a top view of fins on a substrate, according to anexample embodiment.

FIG. 1b depicts a cross-sectional view along the Y₁ axis of FIG. 1a offins on a substrate, according to an example embodiment.

FIG. 1c depicts a cross-sectional view along the X axis of FIG. 1a offins on a substrate, according to an example embodiment.

FIG. 1d depicts a cross-sectional view along the Y₂ axis of FIG. 1a offins on a substrate, according to an example embodiment.

FIG. 2a depicts a top view following deposition of a gate dielectric, anetch stop and a dummy layer, according to an example embodiment.

FIG. 2b depicts a cross-sectional view along the Y₁ axis of FIG. 2afollowing deposition of a gate dielectric, an etch stop and a dummylayer, according to an example embodiment.

FIG. 2c depicts a cross-sectional view along the X axis of FIG. 2afollowing deposition of a gate dielectric, an etch stop and a dummylayer, according to an example embodiment.

FIG. 2d depicts a cross-sectional view along the Y₂ axis of FIG. 2afollowing deposition of a gate dielectric, an etch stop and a dummylayer, according to an example embodiment.

FIG. 3a depicts a top view following patterning a dummy inner gate,according to an example embodiment.

FIG. 3b depicts a cross-sectional view along the Y₁ axis of FIG. 3afollowing patterning a dummy inner gate, according to an exampleembodiment.

FIG. 3c depicts a cross-sectional view along the X axis of FIG. 3afollowing patterning a dummy inner gate, according to an exampleembodiment.

FIG. 3d depicts a cross-sectional view along the Y₂ axis of FIG. 3afollowing patterning a dummy inner gate, according to an exampleembodiment.

FIG. 4a depicts a top view following depositing an outer gate dummylayer, according to an example embodiment.

FIG. 4b depicts a cross-sectional view along the Y₁ axis of FIG. 4afollowing depositing an outer gate dummy layer, according to an exampleembodiment.

FIG. 4c depicts a cross-sectional view along the X axis of FIG. 4afollowing depositing an outer gate dummy layer, according to an exampleembodiment.

FIG. 4d depicts a cross-sectional view along the Y₂ axis of FIG. 4afollowing depositing an outer gate dummy layer, according to an exampleembodiment.

FIG. 5a depicts a top view following formation of the outer dummy gate,according to an example embodiment.

FIG. 5b depicts a cross-sectional view along the Y₁ axis of FIG. 5afollowing formation of the outer dummy gate, according to an exampleembodiment.

FIG. 5c depicts a cross-sectional view along the X axis of FIG. 5afollowing formation of the outer dummy gate, according to an exampleembodiment.

FIG. 5d depicts a cross-sectional view along the Y₂ axis of FIG. 5afollowing formation of the outer dummy gate, according to an exampleembodiment.

FIG. 6a depicts a top view following formation of a hardmask above theouter dummy gate, according to an example embodiment.

FIG. 6b depicts a cross-sectional view along the Y₁ axis of FIG. 6afollowing formation of a hardmask above the outer dummy gate, accordingto an example embodiment.

FIG. 6c depicts a cross-sectional view along the X axis of FIG. 6afollowing formation of a hardmask above the outer dummy gate, accordingto an example embodiment.

FIG. 6d depicts a cross-sectional view along the Y₂ axis of FIG. 6afollowing formation of a hardmask above the outer dummy gate, accordingto an example embodiment.

FIG. 7a depicts a top view following forming a gate dielectric,according to an example embodiment.

FIG. 7b depicts a cross-sectional view along the Y₁ axis of FIG. 7afollowing forming a gate dielectric, according to an example embodiment.

FIG. 7c depicts a cross-sectional view along the X axis of FIG. 7afollowing forming a gate dielectric, according to an example embodiment.

FIG. 7d depicts a cross-sectional view along the Y₂ axis of FIG. 7afollowing forming a gate dielectric, according to an example embodiment.

FIG. 8a depicts a top view following source/drain formation, accordingto an example embodiment.

FIG. 8b depicts a cross-sectional view along the Y₁ axis of FIG. 8afollowing source/drain formation, according to an example embodiment.

FIG. 8c depicts a cross-sectional view along the X axis of FIG. 8afollowing source/drain formation, according to an example embodiment.

FIG. 8d depicts a cross-sectional view along the Y₂ axis of FIG. 8afollowing source/drain formation, according to an example embodiment.

FIG. 9a depicts a top view following exposing the outer dummy gate,according to an example embodiment.

FIG. 9b depicts a cross-sectional view along the Y₁ axis of FIG. 9afollowing exposing the outer dummy gate, according to an exampleembodiment.

FIG. 9c depicts a cross-sectional view along the X axis of FIG. 9afollowing exposing the outer dummy gate, according to an exampleembodiment.

FIG. 9d depicts a cross-sectional view along the Y₂ axis of FIG. 9afollowing exposing the outer dummy gate, according to an exampleembodiment.

FIG. 10a depicts a top view following removing the outer dummy gate,according to an example embodiment.

FIG. 10b depicts a cross-sectional view along the Y₁ axis of FIG. 10afollowing removing the outer dummy gate, according to an exampleembodiment.

FIG. 10c depicts a cross-sectional view along the X axis of FIG. 10afollowing removing the outer dummy gate, according to an exampleembodiment.

FIG. 10d depicts a cross-sectional view along the Y₂ axis of FIG. 10afollowing removing the outer dummy gate, according to an exampleembodiment.

FIG. 11a depicts a top view following removing a portion of the etchstop, according to an example embodiment.

FIG. 11b depicts a cross-sectional view along the Y₁ axis of FIG. 11afollowing removing a portion of the etch stop, according to an exampleembodiment.

FIG. 11c depicts a cross-sectional view along the X axis of FIG. 11afollowing removing a portion of the etch stop, according to an exampleembodiment.

FIG. 11d depicts a cross-sectional view along the Y₂ axis of FIG. 11afollowing removing a portion of the etch stop, according to an exampleembodiment.

FIG. 12a depicts a top view following depositing a first workfunctionmetal, according to an example embodiment.

FIG. 12b depicts a cross-sectional view along the Y₁ axis of FIG. 12afollowing depositing a first workfunction metal, according to an exampleembodiment.

FIG. 12c depicts a cross-sectional view along the X axis of FIG. 12afollowing depositing a first workfunction metal, according to an exampleembodiment.

FIG. 12d depicts a cross-sectional view along the Y₂ axis of FIG. 12afollowing depositing a first workfunction metal, according to an exampleembodiment.

FIG. 13a depicts a top view following removing an inner dummy gate,according to an example embodiment.

FIG. 13b depicts a cross-sectional view along the Y₁ axis of FIG. 13afollowing removing an inner dummy gate, according to an exampleembodiment.

FIG. 13c depicts a cross-sectional view along the X axis of FIG. 13afollowing removing an inner dummy gate, according to an exampleembodiment.

FIG. 13d depicts a cross-sectional view along the Y₂ axis of FIG. 13afollowing removing an inner dummy gate, according to an exampleembodiment.

FIG. 14a depicts a top view following depositing a second workfunctionmetal, according to an example embodiment.

FIG. 14b depicts a cross-sectional view along the Y₁ axis of FIG. 14afollowing depositing a second workfunction metal, according to anexample embodiment.

FIG. 14c depicts a cross-sectional view along the X axis of FIG. 14afollowing depositing a second workfunction metal, according to anexample embodiment.

FIG. 14d depicts a cross-sectional view along the Y₂ axis of FIG. 14afollowing depositing a second workfunction metal, according to anexample embodiment.

FIG. 15 depicts a cross-sectional view along the Y₁ axis of FIG. 14acontaining dimensional markings of the FET gate structure, according toan example embodiment.

FIG. 16 depicts an embodiment of FIG. 15 using nFET workfunction metals,according to an example embodiment.

FIG. 17 depicts an embodiment of FIG. 15 using pFET workfunction metals,according to an example embodiment.

Elements of the figures are not necessarily to scale and are notintended to portray specific parameters of the invention. For clarityand ease of illustration, dimensions of elements may be exaggerated. Thedetailed description should be consulted for accurate dimensions. Thedrawings are intended to depict only typical embodiments of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein withreference to the accompanying drawings, in which exemplary embodimentsare shown. This disclosure may, however, be embodied in many differentforms and should not be construed as limited to the exemplaryembodiments set forth herein. Rather, these exemplary embodiments areprovided so that this disclosure will be thorough and complete and willconvey the scope of this disclosure to those skilled in the art. In thedescription, details of well-known features and techniques may beomitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, terms such as “upper”,“lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing figures. Terms such as “above”,“overlying”, “atop”, “on top”, “positioned on” or “positioned atop” meanthat a first element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure may be present between the first element andthe second element. The term “direct contact” means that a firstelement, such as a first structure, and a second element, such as asecond structure, are connected without any intermediary conducting,insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

Gate-Induced Drain Leakage (GIDL) is a component of leakage from MOSFETdevices. The effect of GIDL is more prevalent at higher VDD and lowergate voltage (V_(g)) of such devices. Traditionally, increased dopingdensities of the source/drain region of the MOSFET device was used tosuppress such GIDL. However, GIDL worsens with scaled inversion layerthickness (T_(inv)), which is a byproduct of miniaturization of devicecomponents. Further, such miniaturization and device geometries make itincreasingly difficult to rectify the losses through additional doping.By modifying the T_(inv) near the source/drain of the MOSFET, the GIDLof such devices may be reduced.

Referring to FIG. 1a-1d , a first fin 102 and a second fin 104 arelocated on a substrate 100. An STI layer 110 may be located on thesubstrate 100 and isolate the first fin 102 and the second fin 104.According to an exemplary embodiment, substrate 100 is a bulksemiconductor wafer, such as a bulk silicon (Si), bulk germanium (Ge),and/or bulk III-V semiconductor wafer. Alternatively, substrate 100 canbe a semiconductor-on-insulator (SOI) wafer. A SOI wafer includes a SOIlayer separated from an underlying substrate by a buried insulator. Whenthe buried insulator is an oxide it is referred to herein as a buriedoxide or BOX. The SOI layer can include any suitable semiconductor, suchas Si, Ge, SiGe, and/or a III-V semiconductor. Substrate 100 may alreadyhave pre-built structures (not shown) such as transistors, diodes,capacitors, resistors, interconnects, wiring, etc. The first fin 102 andthe second fin 104 may be previously formed from the bulk substrate 100through patterning and removal (e.g., sidewall image transfer) and/ordeposition techniques (e.g., epitaxial growth). STI layer 110 may be anysuitable dielectric capable of isolation of the first fin 102 and thesecond fin 104 such as, for example, silicon oxides, silicon nitrides,silicon oxynitrides.

Referring to FIG. 2a-2d , a gate dielectric layer 120, an etch stoplayer 130, and a dummy gate layer 140 may be deposited. The gatedielectric layer 120 may be a high-k material, including but not limitedto metal oxides such as hafnium oxide (e.g., HfO₂), hafnium siliconoxide (e.g., HfSiO₄), hafnium silicon oxynitride (HfSixO_(y)N_(z)),lanthanum oxide (e.g., La₂O₃), lanthanum aluminum oxide (e.g., LaAlO₃),zirconium oxide (e.g., ZrO₂), zirconium silicon oxide (e.g., ZrSiO₄),zirconium silicon oxynitride (ZrSixOyNz), tantalum oxide (e.g., TaO₂,Ta₂O₅), titanium oxide (e.g., TiO₂), barium strontium titanium oxide(e.g., BaTiO₃—SrTiO₃), barium titanium oxide (e.g., BaTiO₃), strontiumtitanium oxide (e.g., SrTiO₃), yttrium oxide (e.g., Y₂O₃), aluminumoxide (e.g., Al₂O₃), lead scandium tantalum oxide(Pb(Sc_(x)Ta_(1-x))O₃), and lead zinc niobate (e.g., PbZn_(1/3)Nb_(2/3)O₃). The high-k dielectric material may further include dopants such aslanthanum and/or aluminum. The stoichiometry of the high-k dielectricmaterial may vary. A process such as CVD, ALD or PVD can be employed todeposit gate dielectric layer 120. According to an exemplary embodiment,gate dielectric layer 120 has a thickness of from about 1 nanometer (nm)to about 5 nm and ranges therebetween.

An etch stop layer 130 may be deposited. Etch stop layer 130 may be anymaterial capable of protecting the underlying gate dielectric layer 120during etching process occurring above the etch stop layer 130. Forexample, the material of the etch stop layer 130 may be TiN. The etchstop layer 130 may be deposited using a process such as CVD, ALD or PVD.

The dummy gate layer 140 may be deposited on the etch stop layer 130. Insuch embodiments, the dummy gate layer 140 may be made of any suitablesacrificial material, for example, amorphous or polycrystalline silicon.The dummy gate layer 140 may be deposited by any suitable depositiontechnique known in the art, including atomic layer deposition (ALD),chemical vapor deposition (CVD), physical vapor deposition (PVD),molecular beam deposition (MBD), pulsed laser deposition (PLD), orliquid source misted chemical deposition (LSMCD).

Referring to FIG. 3a-3d , a gate may be patterned into the dummy gatelayer 140, forming a dummy inner gate 145 and an inner gate hardmask150. A hardmask layer (not shown) may be formed using ALD deposition.The hardmask layer may be formed from, for example, Titanium Nitride orSilicon Nitride. Formation of the dummy inner gate 145 and an inner gatehardmask 150 may be accomplished by lithographic patterning of theregions, and subsequently etching away the dummy gate layer 140 andhardmask layer from the unpatterned areas. Following patterning andremoval the dummy inner gate 145 and an inner gate hardmask 150 areformed from the dummy gate layer 140 and the hardmask layer. Patterningmay be accomplished by depositing a lithographic material (e.g., aphotoresist) and exposing the material with a suitable wavelength oflight, according to the desired pattern. Etching may be performed toremove material not beneath the patterned lithographic material usingany suitable technique, such as, for example, reactive ion etching (RIE)or wet stripping. The pattern for dummy inner gate 145 may create astructure having a width of about 10 to about 20 nm.

Referring to FIG. 4a-4d , a dummy outer gate layer 160 may be formed.Dummy outer gate layer 160 may be formed by a conformal deposition onthe surface of the structure of FIG. 3a-3d . The dummy outer gate layer160 may be made of any suitable sacrificial material capable of beingselectively etched with respect to dummy inner gate 145 such as, forexample, SiGe. The thickness of the deposition of the dummy outer gatelayer 160 may correspond to the final width of first work function metal225 (discussed below with respect to FIG. 12a -12D). The dummy outergate layer 160 may be deposited having a thickness of about 3 to about 5nm.

Referring to FIG. 5a-5d , a dummy outer gate 162 may be formed from thedummy gate layer 160. Formation of dummy outer gate 162 may beaccomplished by removing unwanted material from dummy outer gate layer160 the using an anisotropic etching process such as, for example,reactive ion etching (RIE) or plasma etching. Additionally, inner gatehardmask 150 and dummy outer gate 162 may act as a mask for gatedielectric layer 120 and etch stop layer 130, thereby creating etch stop132 and gate dielectric 122 in the gate region of the device.

Referring to FIG. 6a-6d , planarizing material 170 may be deposited anouter gate hardmask 180 may be formed above the dummy outer gate. Aplanarizing material 170 such as, for example, an organic planarizinglayer (OPL) material may be deposited onto substrate 100 and recessed toa height at or beneath the dummy outer gate 162. A casting process suchas spin coating or spray casting can be employed to deposit theplanarizing material 170 onto the structure of FIG. 5a-5d . Adirectional (anisotropic) etching process such as RIE can be used torecess the planarizing material 170 to the desired height. The outergate hardmask 180 may be formed by conformal deposition of a hardmaskmaterial, followed by removing unwanted material from the conformallayer using an anisotropic etching process such as, for example,reactive ion etching (RIE) or plasma etching. The outer gate hardmask180 may be made of any suitable masking material such as, for example,silicon nitride.

Referring to FIG. 7a-7d , the planarizing material 170 may be removedand a gate spacer 190 may be formed. By way of example only, an OPLplanarizing material 170 may be removed using a process such as ashing.Spacers 190 may be formed adjacent to the dummy outer gate 162 and anouter gate hardmask 180. The spacers 190 may be made of any insulatingmaterial, such as silicon nitride, silicon oxide, silicon oxynitrides,high-k dielectrics (such as those listed above) or a combinationthereof, and may have a thickness ranging from 2 nm to approximately 100nm, preferably approximately 2 nm to approximately 25 nm. The spacers190 may be formed by any method known in the art, including depositing aconformal dielectric layer over the structure depicted in FIG. 6a-6d andremoving unwanted material using an anisotropic etching process such as,for example, reactive ion etching (RIE) or plasma etching. Methods offorming spacers are well-known in the art and other methods areexplicitly contemplated. Further, in various embodiments, the spacers190 may include one or more layers. While the spacers 190 are hereindescribed in the plural, the spacers 190 may be a single spacersurrounding each gate structure.

Referring to FIG. 8a-8d , source/drain (S/D) 200 may be formed in asource/drain region of the first fin 102 and the second fin 104 and ILD210 may be formed above S/D 200 and planarized. The S/D 200 may result asemiconductor material epitaxially grown on the exposed source/drainregion of first fin 102 and second fin 104 and annealed. In an exampleembodiment of a p-FET, the semiconductor material may besilicon-germanium. In such an embodiment, a p-type semiconductormaterial may contain, for example, approximately 20% to approximately100% germanium, approximately 0% to approximately 80% silicon, and maybe doped with p-type dopants such as boron in concentrations rangingfrom approximately 1×10²⁰ atoms/cm³ to approximately 2×10²¹ atoms/cm³.In another example embodiment of an n-FET, the semiconductor materialmay be carbon doped silicon. In such an embodiment, the n-typesemiconductor material may contain, for example, approximately 0.5% toapproximately 2.5% carbon, approximately 97.5% to approximately 99.5%silicon, and may be doped with n-type dopants such as arsenic orphosphorus in concentrations ranging from approximately 1×10²⁰ atoms/cm³to approximately 2×10²¹ atoms/cm³.

Referring to FIG. 9a-9d , dummy outer gate 162 may be exposed using CMP.During CMP, the height of the structure of FIG. 9a-9d may be reduced toremove outer gate hardmask 180, and thereby reducing the total height ofthe structure and exposing a top surface of the dummy outer gate 162.

Referring to FIG. 10a-10d , the dummy outer gate 162 may be selectivelyremoved with respect to dummy inner gate 145. Any suitable methodcapable of selectively removing dummy outer gate 162 with respect todummy inner gate 145 may be used.

Referring to FIG. 11a-11d , the etch stop 132 that was previouslylocated beneath the dummy outer gate 160 may be removed, forming etchstop 134 located only beneath dummy inner gate 145. Etch stop 132 may beremoved using, for example, RIE.

Referring to FIG. 12a-12d , a first workfunction metal 220 may bedeposited in the void created by removing the outer dummy gate from FIG.11a-11d . In forming the first workfunction metal 220, one or morelayers of suitable workfunction metals may be deposited using a processsuch as CVD, ALD or PVD. Following deposition, the metal overburden canbe removed using a process such as CMP. Suitable n-type workfunctionmetals include, but are not limited to, titanium nitride (TiN), tantalumnitride (TaN) and/or aluminum (Al)-containing alloys such as titaniumaluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminumcarbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride(TaAlN), and/or tantalum aluminum carbide (TaAlC). Suitable p-typeworkfunction-setting metals include, but are not limited to, TiN, TaN,and/or tungsten (W). TiN and TaN are relatively thick (e.g., greaterthan about 2 nm) when used as p-type workfunction-setting metals.However, very thin TiN or TaN layers (e.g., less than about 2 nm) mayalso be used beneath Al-containing alloys in n-type workfunction-settingstacks to improve electrical properties such as gate leakage currents.

In an example n-FET embodiment, the first workfunction metal 220 may bea layered stack of TiN/Al-containing alloy/TiN. In such an embodiment,the thickness of the bottom TiN may be about 0.5 to about 1.0 nm, thethickness of the Al-containing alloy may be about 0.5 to about 3.0 nm,and TiN may fill the rest of the cavity. In an example p-FET embodiment,the first workfunction metal 220 may be TiN.

Referring to FIG. 13a-13d , the dummy inner gate 145 and etch stop 134may be removed. For example, anisotropic etch, such as a RIE, may beused to remove the dummy inner gate 145 and the etch stop 134.

Referring to FIG. 14a-14d , a second work function metal 240 may bedeposited with a sacrificial cap 230 located above. A secondworkfunction metal 240 may be deposited in the void created by removingthe outer dummy gate from FIG. 11a-11d . In forming the secondworkfunction metal 240, one or more layers of suitable workfunctionmetals may be deposited using a process such as CVD, ALD or PVD.Following deposition, the metal overburden can be removed using aprocess such as CMP. Suitable n-type workfunction metals include, butare not limited to, titanium nitride (TiN), tantalum nitride (TaN)and/or aluminum (Al)-containing alloys such as titanium aluminide(TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide(TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN),and/or tantalum aluminum carbide (TaAlC). Suitable p-typeworkfunction-setting metals include, but are not limited to, TiN, TaN,and/or tungsten (W). TiN and TaN are relatively thick (e.g., greaterthan about 2 nm) when used as p-type workfunction-setting metals.However, very thin TiN or TaN layers (e.g., less than about 2 nm) mayalso be used beneath Al-containing alloys in n-type workfunction-settingstacks to improve electrical properties such as gate leakage currents.Following deposition of a sacrificial cap 230 may be formed above thegate region. Following the formation of the depicted structure,additional techniques, such as forming electrical connections to S/D 200and the gate, as well as other back end of the line (BEOL) techniquesmay be performed.

In an example n-FET embodiment, the second workfunction metal 240 may bea layered stack of TiN/Al-containing alloy/TiN. In such an embodiment,the thickness of the bottom TiN may be about 1.0 to about 3.0 nm, thethickness of the Al-containing alloy may be about 0.5 to about 5.0 nm,and TiN may fill the rest of the cavity. In such an embodiment, thethickness of the bottom TiN layer of the second workfunction metal 240may be larger than the thickness of the bottom TiN of the firstworkfunction metal 220. In an example p-FET embodiment, the secondworkfunction metal 240 may be a layered stack of TiN/Al-containingalloy/TiN. In such an embodiment, the thickness of the bottom TiN may beabout 3.0 to about 5.0 nm, the thickness of the Al-containing alloy maybe about 0.5 to about 5.0 nm, and TiN may fill the rest of the cavity.

Following the process outlined above, the structure of FIG. 15 may becreated. FIG. 15 depicts a gate region 250 on a substrate 100. The gateregion may contain a first workfunction metal 225 and a second workfunction metal 240 above a gate dielectric 122 located in contact withthe first fin 102. A second workfunction metal 240 may be approximatelycentered over the gate dielectric 122 and may be located on both sidesby a first workfunction metal 225. The overall width W1 of theworkfunction metals may be about 15 to about 20 nm. The secondworkfunction metal 240 may have a width W3 of about 5 to about 10 nm.The first workfunction metal 225 may have a width W2 of about 3 to about5 nm. In such an embodiment, the width W3 of the second workfunctionmetal 240 may be about 50 to about 75% of the overall width W1 of theworkfunction metals. In such an embodiment, the width W2 of the firstworkfunction metal 225 may be about 25 to about 50% of the overall widthW1 of the workfunction metals. Spacers 190 may be located adjacent tothe first workfunction metal 225, and between the first workfunctionmetal 225 and the S/D 200.

Referring to FIG. 16, depicted is an embodiment of the structure of FIG.15 having n-FET workfunction metals discussed above. In the depictedembodiment, first workfunction metal 225 contains the first layer 221 ofthe first workfuncion metal 225, the second layer 222 of the firstworkfuncion metal 225, and the third layer 223 of the first workfuncionmetal 225. As used herein, thickness of a layer is defined as thedistance between the adjacent layers of the layer (e.g., the thicknessof the first layer is the distance between the gate dielectric 122 andthe second layer 222). The first layer 221 may include TiN and thethickness may be about 0.5 to about 1.0 nm. The second layer 222 may inan Al-containing alloy and the thickness may be about 0.5 to about 3.0nm. The third layer 223 may include TiN. In the depicted embodiment,second workfunction metal 240 contains the first layer 241 of the secondworkfunction metal 240, the second layer 242 of the second workfunctionmetal 240, and the third layer 243 of the second workfunction metal 240.The first layer 241 may include TiN and the thickness may be about 1.0to about 3.0 nm. The second layer 242 may in an Al-containing alloy andthe thickness may be about 0.5 to about 5.0 nm. The third layer 243 mayinclude TiN. In such emodiments, the first layer 241 of the secondworkfunction metal 240 may be thicker than the first layer 221 of thefirst workfunction metal 220. Additionally, while FIG. 16 depicts au-shaped workfunction layer due to the conformal deposition, othergeometries are contemplated having the thicknesses described above.

Referring to FIG. 16, depicted is an embodiment of the structure of FIG.15 having n-FET workfunction metals discussed above. In the depictedembodiment, first workfunction metal 225 is depicted as outer nFETworkfunction metal 226. In this embodiment, outer nFET workfunctionmetal 226 may include TiN. In the depicted embodiment, secondworkfunction metal 240 contains the first layer 241 of the secondworkfunction metal 240, the second layer 242 of the second workfunctionmetal 240, and the third layer 243 of the second workfunction metal 240.The first layer 241 may include TiN and the thickness may be about 0.5to about 1.0 nm. The second layer 242 may in an Al-containing alloy andthe thickness may be about 0.5 to about 3.0 nm. The third layer 243 mayinclude TiN. In such emodiments, the first layer 241 of the secondworkfunction metal 240 may be thicker than the first layer 221 of thefirst workfunction metal 220. Additionally, while FIG. 16 depicts au-shaped workfunction layer due to the conformal deposition, othergeometries are contemplated having the thicknesses described above.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration but are not intended tobe exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableother of ordinary skill in the art to understand the embodimentsdisclosed herein. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustratedbut fall within the scope of the appended claims.

What is claimed is:
 1. A method of forming a semiconductor structurecomprising: forming a gate dielectric on a gate region of a substrate;forming an inner dummy gate on a first portion of the gate dielectric;forming an outer dummy gate adjacent to the inner dummy gate on a secondportion of the gate dielectric; forming spacers adjacent to the outerdummy gate; removing the outer dummy gate and depositing a first workfunction metal; and removing the inner dummy gate and depositing asecond work function metal.
 2. The method of claim 1, wherein a width ofthe inner dummy gate is about 5.0 to about 10.0 nm.
 3. The method ofclaim 1, wherein a width of the outer dummy gate is about 3.0 to about5.0 nm.
 4. The method of claim 1, wherein a width of the inner dummygate is about 50% to about 75% nm of a width of the gate region.
 5. Themethod of claim 1, wherein a width of the outer dummy gate is about 25%to about 50% nm of a width of the gate region.
 6. The method of claim 1,wherein the semiconductor structure is a nFET.
 7. The method of claim 6,wherein the first work function metal comprises: a bottom layercomprising TiN; an intermediate layer comprising an Al-containing alloy;and a top layer comprising TiN.
 8. The method of claim 7, wherein thesecond work function metal comprises: a bottom layer comprising TiN; anintermediate layer comprising an Al-containing alloy; and a top layercomprising TiN.
 9. The method of claim 8, wherein a thickness of thebottom layer of the second work function metal is larger than athickness of the bottom layer of the first work function metal.
 10. Themethod of claim 8, wherein a thickness of the bottom layer of the secondwork function metal is about 1.0 to about 3.0 nm.
 11. The method ofclaim 8, wherein a thickness of the bottom layer of the first workfunction metal is about 0.5 to about 1.0 nm.
 12. The method of claim 1,wherein the semiconductor structure is a pFET.
 13. The method of claim12, wherein the first work function metal comprises TiN.
 14. The methodof claim 13, wherein the second work function metal comprises: a bottomlayer comprising TiN; an intermediate layer comprising an Al-containingalloy; and a top layer comprising TiN.
 15. A semiconductor structurecomprising: a gate dielectric located on a substrate, wherein the gatedielectric defines a gate region of the substrate; a first work functionmetal located on a first portion of the gate dielectric; and a secondwork function metal located on a second portion of the gate dielectric,wherein the first work function metal sandwiches the second workfunction metal.
 16. The structure of claim 15, wherein a width of thefirst work function metal is about 3.0 to about 5.0 nm.
 17. Thestructure of claim 15, wherein a width of the first work function metalis about 25% to about 50% of the width of the gate region.
 18. Thestructure of claim 15, wherein the semiconductor structure is a nFET,wherein the first work function metal comprises a bottom layercomprising TiN, an intermediate layer comprising an Al-containing alloy,and a top layer comprising TiN, and wherein the second work functionmetal comprises a bottom layer comprising TiN, an intermediate layercomprising an Al-containing alloy, and a top layer comprising TiN. 19.The structure of claim 18, wherein a thickness of the bottom layer ofthe second work function metal is larger than a thickness of the bottomlayer of the first work function metal.
 20. The structure of claim 15,wherein the semiconductor structure is a nFET, wherein the first workfunction metal comprises TiN, and wherein the second work function metalcomprises a bottom layer comprising TiN, an intermediate layercomprising an Al-containing alloy, and a top layer comprising TiN.